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60911 sy/70208 ms / 51408 ms pc 20080331-s00006 no.a1173-1/11 specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use. LV4912GP overview the LV4912GP is analog input type digital power amplifier with 2w 1 channel. by using an original feed back technology, it improves sound quality through it is class-d power amplifier and the lc filter in the output stage can be deleted as application. features ? enabling output lc filter-less. ? class-d amplifier system of the output btl type. ? improve the sound quality by the use of original feedback technology. ? realized high efficien cy class-d amplifier. ? reduce the pop sound at on/off state by the use of soft mute function. ? full complement of built-in protection circuits : over cu rrent protection, thermal protection, and low power supply voltage protection circuits. ? internal oscillation frequency : 280khz functions ? output power : 2w(vd = 5v, r l = 4 , thd + n = 10%) ? thd + n : 0.4% (vd = 5v, r l = 4 , fin = 1khz, p o = 1w, filter : aes17) ? noise : 70 vrms (filter : din audio) ? package vct24 (3.5 3.5) bi-cmos lsi class-d audio power amplifier btl 2w 1ch orderin g numbe r : ena1173b
LV4912GP no.a1173-2/11 specifications maximum ratings at ta = 25 c parameter symbol conditions ratings unit maximum supply voltage vd externally applied voltage 6 v allowable power dissipation pd max mounted on a board * 1 w operating temperature topr -20 to +75 c storage temperature tstg -40 to +150 c ? when mounted on the specified printed circuit board : 40mm 50mm 1.6mm, glass epoxy recommended operation conditions at ta = 25 c parameter symbol conditions ratings unit min typ max supply voltage range vd externally applied voltage 2.7 5 5.5 v load impedance renge r l speaker load 4 electrical characteristics at ta = 25 c, vd = 5v, r l = 4 , l = 22 h, c = 0.33 f parameter symbol conditions ratings unit min typ max operating current standby current ist stby = l, mute = l, lc less, r l = open 1 8 a mute current imute stby = h, mute = l, lc less, r l = open 4.5 7.5 ma quiescent current i cco stby = h, mute = h, lc less, r l = open 6 10 ma main amplifier voltage gain vg fin = 1khz, v o = 0dbm 21.5 23.5 25.5 db total harmonic distortion thd+n p o = 1w, fin = 1khz, aes17 0.4 0.7 % output power p o thd+n = 10%, fin = 1khz, aes17 1.6 2 w ripple rejection ratio svrr fr = 100hz, vr = -15dbm, rg = 0, din audio 50 60 db noise v no rg = 0, din audio 70 210 vrms digital input high-level output voltage v ih stby pin, mute pin 3 v low-level output voltage v il stby pin, mute pin 0.3 v protection circuit power supply voltage drop protection circuit upper limit value uv_upper vd pin voltage monitor 2.3 v power supply voltage drop protection circuit lower limit value uv_lower vd pin voltage monitor 2.2 v note : the values of these characteristics were measured in the sanyo test environmen t. the actual values in an end system will vary depending on the printed circuit board pattern, the external components actually used, and other factors. package dimensions unit : mm (typ) 3322a pd max -- ta ambient temperature, ta ? c allowable power dissipation, pd max ? w 0 1 0.6 0.8 0.4 0.2 1.2 ? 20 80 0.11 0.6 75 60 20 40 010 0 specified board independent ic specified board : 40 50 1.6mm 3 glass epoxy sanyo : vct24(3.5x3.5) 3.5 3.5 0.4 0.8 (0.035) 1 2 24 0.5 (0.5) top view side view side view bottom view (0.125) (c0.17) (0.13) 0.25
LV4912GP no.a1173-3/11 LV4912GP customer bread board rev.1.0 size : 40mm 50mm 1.6mm pattern top layer bottom layer
LV4912GP no.a1173-4/11 block diagram and application circuit example (r l = 4 ) LV4912GP application (r l = 4 ) part list parts name part no. description function c vd c1 power supply capacitor for vd c vd c2, c3 high-frequency cut capacitor for vd c in c4, c5 input capacitor c mute c6 capacitor for soft mute c biascap c7 input coupling capacitor for internal power supply (vbias) l o l1, l2 output l. p. f. coil c o c8, c9, c10 output l. p. f. capacitor pin assignments pre_vd pre_gnd v in - v in + nc nc pwr_vd test2 stby test1 nc top view mute 2 3 5 4 1 24 23 22 21 20 19 789101112 6 17 16 14 15 18 13 out + pwr_gnd nc out - nc nc nc nc nc biascap nc mutecap receiver sequence vbias c6 1 f c7 1 f c5 1 f c3 1 f c4 1 f iref supply under voltage protection over current protection thermal protection v cc control delay outputstage outputstage 0-5v stby in + pre_vd in - 0-5v mute mutecap biascap + pre_gnd pwr_vd pwr_gnd out + out - c1 100 f c10 1 f c8 0.33 f 22 h l1 22 h l2 c9 0.33 f vd rl c2 1 f
LV4912GP no.a1173-5/11 pin equivalent circuit pin no. pin name i/o description equivalent circuit 1 nc no connection 2 pre_vd power supply pin 3 pre_gnd pre ground 4 v in + i input plus 30k 300 vbias gnd vd 4 5 v in - i input minus 30k 300 vbias gnd vd 5 6 nc no connection 7 nc no connection 8 nc no connection 9 nc no connection 10 biascap o internal power supply decoupling capacitor connection 90k 100k 200k gnd vd 10 11 nc no connection 12 mutecap o mute capacitor connection gnd 12 vd 200k v cc 13 mute i mute control pin 100k 200k gnd 13 vd v cc continued on next page.
LV4912GP no.a1173-6/11 continued from preceding page. pin no. pin name i/o description equivalent circuit 14 stby i standby control pin 100k 200k gnd 14 vd 15 test1 test pin 16 test2 test pin 17 pwr_vd power supply pin 18 nc no connection 19 nc no connection 20 nc no connection 21 out- o output pin, minus gnd 21 vd 22 pwr_gnd power ground 23 out + o output pin, plus gnd 23 vd 24 nc no connection
LV4912GP no.a1173-7/11 description functions 1. system standby each bias can be turned on/off by switching the stby pin (pin 14) into high or low. the bias is turned off when the stby pin is low. conversely, the bias is turned on when the stby pin is high. stby pin (pin 14) bias condition high on low off 2. mute function the mute of the output and reduction of power-on popping noise are mainly performed by the use of this function. by switching between high and low on the mute pin (pin 13), the output can be muted. the mute pin enters the mute mode (pwm output stops) when the mute pin is low. also the mute pin enters the operation mode (normal operations) when the mute pin is high. mute pin (pin 13) conditions high operation mode low mute mode we recommend the following sequence for reduction of the popping noise when power is on/off. also, we recommend the following on time and off time when p.4 the application circuit is used. (1) power on sequence the on time should secure more than 150msec for reduction of the popping noise. on time stby mute mutecap output pin internal power supply
LV4912GP no.a1173-8/11 (2) power down sequence the off time should secure more than 100msec for reduction of the popping noise. capacitors for power supply and pin arrangement 1. capacitors for power supply the capacitors c2 and c3 for power su pply connected between ic pins must be inserted using the shortest lines possible. 2. pin arrangement of the test pins (pins 15 and 16) the test pins (pins 15 and 16) are used as pins for testing before shipment. these pins are not used normally. therefore, these pins must be left open if the pin arrangement is not performed. please make sure to connect these pins to gnds if the pin arrangement is performed. off time stby mute mutecap output pin internal power supply 3 2 pre_gnd pre_vd c3 1 f 22 17 pwr_gnd pwr_vd c2 1 f
LV4912GP no.a1173-9/11 general characteristics 4 3.5 3 4.5 5 5.5 0 2 4 6 10 8 12 14 2 3 5 7 16 2.5 4 3.5 3 4.5 5 5.5 6 supply voltage, vd ? v quiescent current, i cco ?ma thd+n ? p o 0.01 0.1 2 3 5 7 2 3 5 7 1 10 0.001 23 57 0.01 23 57 0.1 23 57 23 57 1 3456 10 output power, p o ?w total harmonic distortion, thd+n ? % p o ? vd 0 0.5 1 1.5 2 2.5 27 supply voltage, vd ? v output power, p o ?w 23 57 0.01 23 57 0.1 23 57 23 57 1 thd+n ? p o 0.01 2 3 5 7 2 3 5 7 0.1 2 3 5 7 0.1 10 0.001 10 output power, p o ?w total harmonic distortion, thd+n ? % pca02904 2.5 6 supply voltage, vd ? v mute current, imute ? ma imute ? vd i cco ? vd vd = 5v aes17 0 0.5 1 1.5 2 2.5 3 3.5 234567 supply voltage, vd ? v output power, p o ?w p o ? vd 0.001 2 3 5 7 0.01 2 3 5 7 0.1 2 3 5 7 2 3 5 7 1 10 10 25 37 2 5 37 100 1000 input voltage, v in ? mvp output power, p o ?w p o ? v in 0.14 0.16 ist ? vd 0 0.02 0.04 0.06 0.08 0.1 0.12 0.18 1 2 3 4 5 6 0 7 2.5 4 3.5 3 4.5 5 5.5 6 supply voltage, vd ? v standby current, ist ? a r l = 4 stbt = l, mute = l r l = 4 stbt = h, mute = h vd = 5v r l = 4 aes17 vd = 5v r l = 4 aes17 vd = 5v r l = 8 aes17 vd = 5v r l = 8 aes17 r l = 4 stbt = l, mute = l thd = 10% f = 6.67khz f = 100hz f = 1khz f = 6.67khz f = 100hz f = 1khz thd = 1% thd = 10% thd = 1% r l = 4 r l = 8
LV4912GP no.a1173-10/11 temperature characteristics 23 57 23 57 100 23 57 23 57 10k 1k ? 60 ? 50 ? 40 ? 30 ? 20 ? 10 0 10 20 1 2 3 4 5 30 10 3 257 3 257 100 3 257 10k 3 257 1k 100k frequency, f ? hz phase ? deg imute ? ta 0 6 ? 50 ? 25 0 25 50 75 0.5 1 1.5 100 allowable temperature, ta ? c mute current, imute ? ma pd ? p o 0 0.2 0.4 0.6 0.8 1 1.2 02 output power, p o ?w power dissipation, pd ? w ? 25 0 25 50 75 i cco ? ta 0 2 4 6 8 10 12 14 16 18 20 ? 50 100 allowable temperature, ta ? c quiescent current, i cco ?ma 10 100 k frequency, f ? hz response ? db response ? f phase ? f 0 20 40 60 80 100 0 0.5 1 1.5 2 output power, p o ?w efficiency ? % efficiency ? p o 0 10 20 30 40 50 60 70 0.1 257 3 1 257 3 10 257 3257 3 100 1000 bias capacitance, bias cap ? f ripple rejection ratio, svrr ? db svrr ? biascap thd+n ? f 0.001 2 3 5 7 0.01 2 3 5 7 0.1 2 3 5 7 2 3 5 7 1 10 0 5 ? 20 ? 15 ? 10 ? 5 10 10 100 23 57 23 57 23 57 23 57 1k 10k 100k frequency, f ? hz total harmonic distortion, thd+n ? % vd = 5v r l = 4 p o = 1w aes17 vd = 5v r l = 4 rg = 0 stby = h mute = l vd = 5v r l = 4 rg = 0 stby = h mute = h vd = 5v r l = 4 p o = 1w aes17 vd = 5v aes17 vd = 5v aes17 vd = 5v r l = 4 p o = 1w aes17 vd = 5v r l = 4 vr = -15dbm din audio r l = 4 r l = 8 r l = 4 r l = 8
LV4912GP ps no.a1173-11/11 sanyo semiconductor co.,ltd. assumes no responsib ility for equipment failures that result from using products at values that exceed, even momentarily, rate d values (such as maximum ra tings, operating condition ranges, or other parameters) listed in products specif ications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qual ity high-reliability products, however, any and all semiconductor products fail or malfunction with some probabi lity. it is possible that these probabilistic failures or malfunction could give rise to acci dents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. when designing equipment, adopt safety measures so that these kinds of accidents or e vents cannot occur. such measures include but are not limited to protective circuits and error prevention c ircuits for safe design, redundant design, and structural design. upon using the technical information or products descri bed herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable f or any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. information (including circuit diagr ams and circuit parameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equi pment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor c o.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities conc erned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any in formation storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. this catalog provides information as of june, 2011. specifications and information herein are subject to change without notice. 0255075 20 21 22 23 24 25 ? 50 ? 25 25 0 50 75 100 allowable temperature, ta ? c voltage gain, vg ? db ? 50 ? 25 100 allowable temperature, ta ? c output power, p o ?w p o ? ta vg ? ta 0 10 20 30 40 50 60 70 80 90 ? 50 ? 25 50 25 0 75 100 allowable temperature, ta ? c noise, vno ? vrms vno ? ta 0.1 0.2 0.3 0.4 0.5 0.6 0.7 thd+n ? ta 0 0.8 0.5 1.5 2.0 2.5 1.0 0 3.0 ? 50 ? 25 0 25 50 75 100 allowable temperature, ta ? c total harmonic distortion, thd+n ? % vd = 5v vd = 3.6v vd = 3v vd = 5v r l = 4 p o = 1w fin = 1khz aes17 vd = 5v r l = 4 v in = 0dbm din audio vd = 5v r l = 4 rg = 0 r l = 4 fin = 1khz thd+n = 10% aes17

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